1. Field of the Invention
The present invention relates to a data processor for high-speed digital signal processing and a method of processing data for high-speed digital signal processing.
2. Description of the Background Art
Digital signal processors (DSPs) having an architecture suitable for signal processing have been used as data processors designed specifically for high-speed digital signal processing. These DSPs execute processing frequently used in signal processing such as a multiply-add operation at high speeds. An example of a DSP is Motorola DSP56000. The DSP56000 includes two address pointers, two data memories, and a multiply-add operation unit. Parallel loading of data (e.g., the load of coefficients and data) from two 1-word memories specified respectively by the address pointers, updating of the two address pointers, and the execution of the combined multiply-add operation allows the multiply-add operation to be executed with a high throughput (See DSP56000 Digital Signal Processor Family Manual, 1992). In this manner, the DSP normally has two memories. Data are distributed to either of the memories. Some DSPs use a 2-port RAM for efficient data transfer.
An example of microprocessors incorporating the DSP function includes Motorola CPU16. The CPU16 may repeatedly perform the multiply-add operation and 2-word load in response to one RMAC instruction. However, the CPU16 wherein one multiply-add operation requires 12 cycles is difficult to achieve the performance competing with the DSPs (CPU16 Reference Manual, 1993).
In recent years, some microprocessors have been intended for implementing signal processing by means of software as the operating frequency improves. To improve the arithmetic performance, some of the microprocessors additionally provide the multiply-add operation instructions and make the most of sophisticated parallel processing techniques such as superpipeline and superscalar to achieve DSP-level performance. For example, PowerPC603 (Motorola and IBM) may execute a single-precision floating-point multiply-add operation with one clock cycle throughput by using 3-stage pipeline processing. This requires the amount of hardware and significantly complicated control. To perform one multiply-add operation for each clock cycle, one clock cycle requires 2-word data. The PowerPC603 may load a maximum of one word for each clock cycle, resulting in an insufficient supply of operands (Proceedings of COMPCON 1994: "The PowerPC603 Microprocessor: A High Performance, Low Power, Superscalar RISC Microprocessor", PowerPC603 RISC Microprocessor User's Manual, 1994).
The DSPs which must include two memories have a complicated memory construction and require very cumbersome data management for distribution of data between the two memories. The use of a 2-port RAM adds to the area and costs of the data processor. Additionally, the DSP is in general an accumulator machine and is difficult to execute complicated data processing.
The microprocessors which require one memory have a relatively simple memory construction. However, the microprocessors are not efficient in signal processing unlike the DSPs wherein hardware directly represents the flow of signal processing. To achieve the DSP-level performance, the state-of-the-art microprocessors require an increased amount of hardware, adding to the costs of the data processor. Further, the microprocessors are difficult to reduce power consumption because of the need for operation at high frequencies.